1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for driving a semiconductor memory device.
2. Related Art
In recent years, there has been known an FBC (floating body cell) memory as a semiconductor memory device expected to replace DRAM. The FBC memory includes a sense amplifier. The sense amplifier is connected to a memory cell through a bit line pair so as to read data stored in the memory cell. During data read or data write, one of the paired bit lines transmits the data to the sense amplifier from the memory-cell-whereas other bit lines transmit a reference voltage to the sense amplifier through a dummy cell.
Furthermore, normally, the sense amplifier includes a current-mirror load circuit constituted by an FET opposite in conduction type to the memory cell. If the memory cell is, for example, an n-FET, the current mirror load circuit is constituted by a p-MOS. During the data read, the current-mirror load circuit applies an equal current to the memory cell and the dummy cell from a high voltage source through a sense node pair, respectively. If it is assumed that the data is “1” when the number of holes of the memory cell is large and that the data is “0” when the number of holes is small, the memory cell that stores the data “1” is lower in threshold voltage than the memory cell that stores the data “0”. In this case, a potential of the sense node that detects the data “1” is lower than that of the sense node that detects the data “0”. Accordingly, if the data is amplified, then the sense node that detects the data “1” is amplified to relatively a low potential and the sense node that detects the data “0” is amplified to relatively a high potential. Namely, during the data read, the data is latched by the sense node pair while the data “0” and the data “1” are inverted. It is, therefore, necessary to invert the connection relationship between the sense node pair and the bit line pair during the data write from that during the data read. To invert the connection relationship between the sense node pair and the bit line pair, it is disadvantageously necessary to provide an additional circuit. Accordingly, as a result, a chip size of an entire semiconductor memory device is disadvantageously made large.
Normally, in the sense amplifier, after the data is amplified, the bit line pair is disconnected from the sense node pair. If a period between the amplification time and the disconnection time is too short or the disconnection time is present prior to the amplification time, a sense node capacity is reduced before the amplification time. Accordingly, the data is apt to be influenced by noise deriving from crosstalk between the sense node pair. This can disadvantageously make the sense amplifier erroneously detect the data. On the other hand, if the period between the amplification time and the disconnection time is too long, the data is latched by the sense nodes in opposite sign. Accordingly, the bit lines can be driven in opposite sign to that of the data to be stored during the data write in a refresh operation. Besides, the refresh operation is disadvantageously elongated and power loss is increased. As can be seen, the relationship between the noise problem and the power loss or the like is a trade-off relationship with respect to timings of data amplification and the disconnection of the bit line pair from the sense node pair (see Japanese Patent Application Laid-open No. 2004-120628).